Semiconductor Engineering

LLM-Powered Automatic VLSI Design Flow Tuning Framework

A new technical paper titled “CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs” was published by researchers at Duke University and Synopsys. “Modern very large-scale ...
Electronic Design

Understanding Low-Power IC Design Techniques

Low-power IC design techniques have been around for quite a while. They weren’t always required, though they were nice to have. The rapid growth of the consumer market for battery-powered devices has ...
EDN

Calypto CTO to Present Low-Power Tutorial During VLSI Conference in India

Calypto™ Design Systems Inc., the leader in sequential analysis technology, announced today that Anmol Mathur, Calypto’s chief technology officer, will present a tutorial on system-on-chip (SoC) power ...
Nature

Gate Sizing and Power Optimization in VLSI Design

Gate sizing is a fundamental technique in VLSI design, where the dimensions of transistors and gates are carefully adjusted to achieve optimal performance, minimise power consumption and reduce delay.
Design-Reuse

Sequence Models IP for SoC Power Design Capability Within NanoCool Low-Voltage Flow

SANTA CLARA, Calif. -- March 5, 2002 --Sequence Design Inc., the SoC Design Closure Company, today announced the addition of IP power modeling to the company's NanoCool initiative, the leading flow ...