This new technical paper titled “RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs” was published by researchers at University ...

Inside, the new Intel Gaudi 3 AI accelerator features two chiplets with 64 tensor processor cores (TPCs, 256x256 MAC structure with FP32 accumulators), eight matrix multiplication engines (MMEs, ...

There has been an ever-growing demand for artificial intelligence and fifth-generation communications globally, resulting in very large computing power and memory requirements. The slowing down or ...

TI has added a dedicated AI accelerator to one of its automotive SoCs for the first time, in a move that perfectly illustrates the growing adoption of deep-learning techniques in automotive advanced ...

SC17 continues their series of Session Previews with discussion with Dr. Catherine Graves from HP Labs about her upcoming Invited Talk on “Computing with Physics: Analog Computation and Neural Network ...

Current custom AI hardware devices are built around super-efficient, high performance matrix multiplication. This category of accelerators includes the host of AI chip startups and defines what more ...

A new photonic chip could run optical neural networks 10 million times more efficiently than conventional chips. The classical physical limit for computing energy is the Landauer limit. Landauer limit ...

Staking a claim to the title of world's fastest 64-bit floating-point coprocessor chip, Clear-Speed Technology's CSX600 can deliver a sustained 25 GFLOPs for DGEMM (matrix multiplication) calculations ...

Sparse matrix computations are pivotal to advancing high-performance scientific applications, particularly as modern numerical simulations and data analyses demand efficient management of large, ...

TI has added a dedicated AI accelerator to one of its automotive SoCs for the first time, in a move that perfectly illustrates the growing adoption of deep learning techniques in automotive ADAS ...