NanoTime is a next-generation transistor-level static timing analysis solution that provides concurrent timing and signal integrity analysis for ASIC designs. Its performance and capacity allow ...

San Mateo, Calif. – InTime Software Inc. will unveil a register-transfer-level timing tool this week intended to help IC designers develop timing-accurate RTL code before they move to synthesis, ...

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...

Magma's Tekton static timing analyzer is a next-generation tool built to handle the exploding number of STA scenarios required in modern SoC design. Static timing analysis (STA) is used throughout ...

Full 3D designs involving logic-on-logic are still in the tire-kicking stage, but gaps in the tooling already are showing up. This is especially evident with static timing analysis (STA), which is ...

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).

The times they are a-changin’. With apologies to Mr. Dylan, the ignition timing of your 4x4s engine is pretty well set. Ignition timing is what is used to make sure that the distributor fires the ...