EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. — Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Design-Reuse

Siemens launches Tessent tool for Verilog and RTL design for test

The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern ...
Electronic Design

First Steps Taken On Road To C Synthesis

Following on the heels of its technology announcement late in 2003, Synfora is now shipping PICO Express, its algorithm-to-tapeout tool that synthesizes C algorithms into Verilog RTL. With the tool's ...
Semiconductor Engineering

Low Power Verification – “X” Marks the Spot

Welcome to a new discussion on a range of topics we think will be interesting to folks who design and verify SoCs. Though the name of this blog denotes two top attributes of SoCs—IP implementation and ...