EDN

Power-savvy tool replaces clock-tree synthesis

EDA start-up Azuro Inc wants to help ASIC designers get a better handle on IC power conservation and ultimately lengthen the runtimes of their wireless applications. Toward that end, the company ...
Semiconductor Engineering

The Problem With Clocks

Clocks are power- and area- hungry, and difficult to distribute in a controlled manner. What is being done to reign in these unwieldy beasts? The synchronous digital design paradigm has enabled us to ...
EDN

Monterey adds Synplicity synthesis to ASIC design flow

SAN MATEO, Calif. — Claiming to have a full RTL-to-GDSII design flow at last, Monterey Design Systems has added logic synthesis to its Dolphin placement and routing system. The Dolphin-RTL synthesis ...
Electronic Design

Virtual Prototyping Makes Its Way To FPGAs

Today's FPGAs offer densities of 10 million gates and clock speeds of 400 MHz. Thus, ASIC design starts are trending down while FPGA design starts are on the rise. What's missing is an EDA tool flow ...
Design-Reuse

Magma and ChipX Team to Deliver Unified RTL-to-GDSII Design Flow for Structured ASIC Platforms

Magma design flow supports ChipX CX5000 and future structured ASIC architectures SANTA CLARA, Calif., September 14, 2004 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design ...
Design-Reuse

Magma and ChipX Extend Integrated RTL-to-GDSII Design Flow to Next-Generation Structured ASIC Designs

Magma Blast Create SA, Blast Fusion SA and ChipX CX6000 Structured ASIC combine to reduce cost and cycle time of high-performance designs SANTA CLARA, Calif., Nov. 9, 2005 - ChipX, the structured ASIC ...